Computing Architectures Software tools and nano-Technologies for Numerical Embedded and Scalable Systems

Chair: Rosa Badia (Barcelona Supercomputing Center)

January 26th, 2012

AGENDA

The day will encompass presentations from each of the 4 FET Teradevice Computing (TERACOMP) projects.

NEW: This is a single file containing all the CASTNESS 12 presentations

8:00 - 8:25	Registration
8:25 - 8:30	Opening and Welcome, Rosa M. Badia
8:30 - 10:00	TRAMS Overview of the TRAMS Project in the second year , Antonio Rubio (UPC) FinFET variability - TCAD based PDK development, Si-Yu Liao (UOG) Variability Assessment for 10nm FinFET SRAM, Miguel MIranda (Imec) Quantitative comparison of proactive and reactive variability compensation technique, S. Ganapathy, (UPC) System Reconfiguration to Face Multicore Reliability and Variability Challenges, Tanausu Ramirez (Intel) Panel of questions about TRAMS Project
10:00 - 10:30	Break
10:30 - 12:00	EURETILE Brain Inspired Many-Tile Experiment: second year overview of EURETILE , Pier S. Paolucci (INFN) Peer-to-peer GPGPU-APENet+connectivity on HPC EURETILE platform, Piero Vicini (INFN) Management of process network dynamism in the distributed application layer, Iuliana Bacivarov (ETHZ) Simulation-based software debugging in many-tile systems, Luis Murillo (RWTH) The use of communication path formalization for driver synthesis in the context of hierarchical heterogeneous systems, Frederic Rousseau (UJF-TIMA) Application-Specific Instruction-set Processors (ASIPs) and related design tools for tiled systems, Gert Goossens (TARGET) EURETILE Specific Questions & Answers Panel discussion about possible interactions with other projects
12:00 - 12:30	Invited Presentation
12:30 - 14:00	Lunch
14:00 - 15:30	TERAFLUX TERAFLUX: exploiting dataflow parallelism in teradevice computing - Year 2, Roberto Giorgi (UNISI) PDF Teraflux Architecture, Skevos Evripidou (UCY) Reliability aspects in Teraflux, Theo Ungerer (U. Augsburg) Teraflux, from the programming model to the execution model Antoniu Pop (INRIA) Panel of questions about Teraflux Project
15:30 - 16:00	Break
16:00 - 17:30	SoOs Overview & Status of S(o)OS (HLRS) New approaches to annotating & identifying concurrency and parallelism on code level (HLRS/UT) Description of resource capabilities using ClASH (UT) Characterization and analysis of pipelined applications on the Intel SCC (SSSA) Rethinking Transactional Memory in the Manycore Context (EPFL) Communication & migration in many-core systems (IT) Small groups break-out to enable specific discussions
17:30	End of Workshop

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Previous Editions

The first year edition was organized by the EURETILE project. This year edition (second year) is organized by the TERAFLUX project. Next years editions will be organized by the other FET Teradevice Computing (TERACOMP) projects .

• First year edition

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Place: PARIS - right after the HiPEAC 2012 Conference

Venue

The conference will take place at Eurosites George V, a modern conference center in Paris's "Triangle d'Or":

http://www.eurosites.fr/en/Eurosites_George_V.php

How to reach

Ideally located between Étoile and Concorde, in the most prestigious business district in Paris, Eurosites George V is easily accessible:

• by metro: George V (line 1), Alma Marceau (line 9)
• by bus: Routes 32, 42, 63, 72, 73, 80 and 92
• car park: Vinci Champs Élysées and Alma George V

Address

Eurosites George V
28 avenue George V - 75008 Paris - France
Tel.: +33 1 53 82 60 00

Accomodation

A number of rooms at negociated prices are available through the HiPEAC website (mention the HIPEAC event). The hotels are located at walking distance from Eurosites George V or within a few stops of the Metro lines 1 and 9.

http://www.hipeac.net/conference/paris/accomodation